1. Field of Use
The present disclosure relates to a multiple bit sigma-delta modulator, such as used for analog to digital converters; and more particularly to the quantizer employed in that modulator.
2. Description of the Related Art
FIG. 1 depicts a multiple bit sigma-delta modulator type analog to digital converter (ADC). In this type of converter, the input signal is applied to a summing stage 11 that is configured to generate a signal as a difference between the analog input signal and a feedback signal. The output of the summing stage is applied to a loop filter 12 that shapes the quantization noise thereby producing a filtered signal. The filtered result is applied as an input signal to a multiple bit quantizer 14 configured to quantize that input signal and apply the result to an encoder 15 which produces a digital value. That digital value is applied to a decimation filter 16. The output of the quantizer 14 also is applied to a feedback circuit that includes a digital to analog converter 18, the analog output of which is fed to the summing stage 11 as the feedback signal.
A concern with respect to this type of ADC is the effect on performance due to common mode voltages when the device operates at relatively low supply voltage levels. The quantizer 14 is typically implemented by a plurality of voltage comparators which compare the signal from the loop filter 12 to different reference voltages produced by a voltage divider formed by a resistor ladder. Each comparator has a pair of differential input lines across which the input signal being processed is applied. The output of a particular one of those comparators has a true state when the following expression is satisfied:((VINP+VCM—IN)−(VINM+VCM—IN))>((VREFP+VCM—REF)−(VREFM+VCM—REF))  (1)where VINP and VINM are voltages present on the two input signal lines of the quantizer, VREFP and VREFM are reference voltages for comparing to VINP and VINM, respectively, VCM—IN is the common mode voltage on the input lines, and VCM—REF is the common mode voltage component of the reference voltages.
When a voltage comparator operates at a relatively high supply voltage, all the terms of equation (1) are determined. In that case, the two common mode input voltage variables (VCM—IN) arithmetically cancel each other and the two common mode reference voltage variables (VCM—REF) arithmetically cancel each other. Thus the comparator trips to a true state in response to the input signals satisfying the following relationship:(VINP−VINM)>(VREFP−VREFM)  (2)which is based solely on the input voltage levels and the reference voltage levels.
However, when the voltage comparators operate at a relatively low supply voltage, as may be required for some circuit applications, some of the comparators may not determine all the terms of equation (1) because their biasing requirements are not fulfilled. A particular comparator may not produce values for the (VINM+VCM—IN) and the (VREFM+VCM—REF) components of that equation. As a result, the common mode voltages do not cancel and that comparator transitions to a true state when the following relationship is satisfied:(VINP+VCM—IN)>(VREFP+VCM—REF)  (3).
Another comparator may not produce values for the (VINP+VCM—IN) and the (VREFP+VCM—REF) components of equation (1). Here too, the common mode voltages do not cancel and the comparator transitions to a true state when the following relationship is satisfied:(VINM+VCM—IN)>(VREFM+VCM—REF)  (4).
In both situations represented by equations (3) and (4), the comparator operation is affected by the common mode voltage components of the input signal and the reference voltages. Therefore, the comparator operation is not defined by expression (2).
It is therefore desirable to remove the effects that the common mode input voltage (VCM—IN) and the common mode reference voltage (VCM—REF) have on ADC performance when the quantizer operates at a relatively low supply voltage. Doing so results in the comparator having an output state based solely on the input voltage levels and the reference voltage levels.